{"number":"US12579074B2","kindCode":"B2","documentType":"grant","title":{"original":"Hardware processor core having a memory sliced by linear address","english":"Hardware processor core having a memory sliced by linear address"},"abstract":{"original":"Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plural…","english":"Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plural…"},"applicants":["Intel Corporation"],"inventors":["Mark Dechene","Ryan Carlson","Sudeepto Majumdar","Rafael Trapani Possignolo","Paula Petrica","Richard Klass","Meenakshi Marathe"],"filingDate":"2022-09-21","publicationDate":"2026-03-17","grantDate":"2026-03-17","verifiedWithOffice":true,"pdfUrl":"https://downloadpatent.com/pdf/US12579074B2.pdf","pages":{"en":"https://downloadpatent.com/patent/US12579074B2","zh-Hant":"https://downloadpatent.com/zh-Hant/patent/US12579074B2","ja":"https://downloadpatent.com/ja/patent/US12579074B2"}}