{"number":"US12638893B2","kindCode":"B2","documentType":"grant","title":{"original":"Heterogeneous processor-based system for dynamically coupling power and clock to a last level cache","english":"Heterogeneous processor-based system for dynamically coupling power and clock to a last level cache"},"abstract":{"original":"Aspects disclosed in the detailed description include a heterogenous processor-based system for dynamically coupling power and clock to a last level cache. The heterogenous processor-based system includes a processing cluster of big cores and little cores. The big cores are coupled to a big core power rail to power its operations. The little cores are coupled to a little core power rail to power its operations. The plurality of big and little cores share a last level cache to read data from and write data to.…","english":"Aspects disclosed in the detailed description include a heterogenous processor-based system for dynamically coupling power and clock to a last level cache. The heterogenous processor-based system includes a processing cluster of big cores and little cores. The big cores are coupled to a big core power rail to power its operations. The little cores are coupled to a little core power rail to power its operations. The plurality of big and little cores share a last level cache to read data from and write data to.…"},"applicants":["QUALCOMM Incorporated"],"inventors":["Bharat Kumar Rangarajan"],"filingDate":"2024-06-10","publicationDate":"2026-05-26","grantDate":"2026-05-26","verifiedWithOffice":true,"pdfUrl":"https://downloadpatent.com/pdf/US12638893B2.pdf","pages":{"en":"https://downloadpatent.com/patent/US12638893B2","zh-Hant":"https://downloadpatent.com/zh-Hant/patent/US12638893B2","ja":"https://downloadpatent.com/ja/patent/US12638893B2"}}