{"number":"US20260161392A1","kindCode":"A1","documentType":"publication","title":{"original":"Apparatus And Method For Memory Alias Disambiguation Training","english":"Apparatus And Method For Memory Alias Disambiguation Training"},"abstract":{"original":"Embodiments of a processor for MAD training comprise: decode circuitry to decode instructions into uops, including a plurality of load and store uops; memory execution circuitry executes the plurality of load uops to load data from a memory subsystem and to execute the plurality of store uops to store data to the memory subsystem; and memory alias disambiguation (MAD) prediction circuitry to make a prediction as to whether a first load uop of the plurality of load uops can be executed prior to execution of a first one or more store uops of the plurality of store uops without causing a conflict…","english":"Embodiments of a processor for MAD training comprise: decode circuitry to decode instructions into uops, including a plurality of load and store uops; memory execution circuitry executes the plurality of load uops to load data from a memory subsystem and to execute the plurality of store uops to store data to the memory subsystem; and memory alias disambiguation (MAD) prediction circuitry to make a prediction as to whether a first load uop of the plurality of load uops can be executed prior to execution of a first one or more store uops of the plurality of store uops without causing a conflict…"},"applicants":["Intel Corporation"],"inventors":["Sudeepto MAJUMDAR","Mark DECHENE","Michael MEEUWSEN","Meenakshi MARATHE","Brendan WEST"],"filingDate":"2024-12-06","publicationDate":"2026-06-11","grantDate":null,"verifiedWithOffice":true,"pdfUrl":"https://downloadpatent.com/pdf/US20260161392A1.pdf","pages":{"en":"https://downloadpatent.com/patent/US20260161392A1","zh-Hant":"https://downloadpatent.com/zh-Hant/patent/US20260161392A1","ja":"https://downloadpatent.com/ja/patent/US20260161392A1"}}