美國
US 12,579,074 B2
Hardware processor core having a memory sliced by linear address
US 12,579,074 B2 是美國專利商標局（USPTO）的核准專利，日期 2026-03-17。申請人：Intel Corporation。PDF 可在本頁下載，未登入每天最多 5 篇。
- 申請人
- Intel Corporation
- 發明人
- Mark Dechene; Ryan Carlson; Sudeepto Majumdar; Rafael Trapani Possignolo; Paula Petrica; Richard Klass; Meenakshi Marathe
- 公開日
- 2026-03-17
- 申請日
- 2022-09-21
- 文件種類
- B2 核准公告
- 也寫作
- US 12,579,074 B2 · US12579074 · 12579074
摘要
Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plural…
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專利局網站： 美國專利商標局（USPTO）