United States
US 12,579,074 B2
Hardware processor core having a memory sliced by linear address
US 12,579,074 B2 is a granted patent from the United States Patent and Trademark Office (USPTO), dated 2026-03-17. Applicant: Intel Corporation. Its PDF downloads from this page without an account, up to 5 a day.
- Applicant
- Intel Corporation
- Inventors
- Mark Dechene; Ryan Carlson; Sudeepto Majumdar; Rafael Trapani Possignolo; Paula Petrica; Richard Klass; Meenakshi Marathe
- Publication date
- 2026-03-17
- Filing date
- 2022-09-21
- Document type
- B2 Granted patent
- Also written as
- US 12,579,074 B2 · US12579074 · 12579074
Abstract
Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plural…
The opening of the abstract. The full text is in the PDF.
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Patent office website: United States Patent and Trademark Office (USPTO)
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